11th International Conference and Exhibition on Device Packaging
Meeting Dates: March 16-19, 2015
WeKoPa Resort, Fountain Hills, Arizona
The Arizona Chapter serves the IMAPS members residing in Arizona and New Mexico. The IMAPS Arizona Chapter promotes and cultivates a local forum for the exchange of technical information and industry solutions relating to microelectronics to help our members and their companies better compete in today’s global economy. The chapter holds technical meetings, plant tours, and networking social events throughout the year.
Presented by Ahmer Syed, Sr. Director, Package Engineering, Qualcomm Technologies, Inc.
Limited PCB real estate and phone thickness constraints pose a number of technical challenges for designing IC packages for mobile applications. While thin packages are required to meet height constraints requirements, room temperature co-planarity and high temperature warpage become critical issues for packages with thin substrate, die, and mold cap. Similarly, while PoP provides numerous benefits from size, height, and business standpoint; poor heat dissipation path limits the device performance for extended period of time. Further, Chip-package interactions and board level reliability continue to be pushed to their limits with increased IO density, both at die and package level.
This presentation will highlight some of these challenges and identify areas where partnership across the supply chain is required to overcome these challenges.
Prior to his current position as Sr. Director at Qualcomm Package Engineering, Mr. Syed spent 16 Years at Amkor Technology where he managed board level and electromigration reliability programs, establishing test methods and test facilities, and supported development of Cu Pillar, PoP, TSV, WLCSP, Flip Chip, CSP, BGA, QFN, Stacked CSP, FusionQuad and various other packages with mechanical and thermal characterization.
Mr. Syed also participates in various industry consortiums and task groups, has chaired JEDEC group for drop and bend test development, and authored JEDEC standards JESD-22-B111 and JESD-22-B113.
Widely recognized as an industry expert in package and board level reliability, mechanical simulation and characterization, solder joint life prediction, stress analysis, electromigration reliability, and package material and design optimization, Mr. Syed is a highly sought after speaker for industry symposiums and has authored and co-authored 50+ technical papers and articles.